1. Field Of The Invention
This invention relates to memory array circuitry and, more particularly, to decoding circuitry which may be used with three levels of voltages to provide accelerated row decoding.
2. History Of The Prior Art
There are a number of types of non-volatile memory arrays utilized to store digital information. Erasable read only memory (EPROM) and extensions of EPROM such as flash EPROM are used for many purposes. In general, such arrays are comprised of many transistors arranged in rows and columns with selection circuitry for determining the particular transistors to access. There has been a general tendency for such arrays (as for all memory arrays) to grow larger by including more and more memory transistors. As the number of transistors in a memory array connected to any selection line (such as a wordline or bitline) increases so does the capacitance affecting the line. This has the general tendency of slowing the rate at which switching can be accomplished.
The typical circuitry for accomplishing wordline decoding in an EPROM or a flash EPROM memory array utilizes a NAND gate as a predecoder circuit. This predecoder circuit is used to select a number of wordlines from a total of all wordlines, and then the individual wordline is selected from that first number of wordlines by one of a plurality of row decoder transistors connected in common to the output of the NAND gate.
In a non-volatile memory array, typically two separate voltage supplies are provided. One voltage supply, Vcc, is typically five volts and is used for reading the contents of the memory array. A second voltage supply, Vpp, is typically twelve volts and is used for programming and erasing the contents of the memory array. The row decoding circuitry must be designed to allow the transfer of both of these voltage levels onto the wordline. Typically, an internal voltage supply node exists which can be switched between the two external voltage supply values. This internal voltage supply node is connected to the row decoding circuitry to supply one or the other of the supply voltages.
The typical NAND gate used as a predecoder in these non-volatile arrays is made of one or more N channel field effect transistors (FETs) with their drain and source terminals connected in series between ground and an output terminal and a P channel field effect transistor with its source and drain terminals connected between a source of voltage (typically the internal voltage supply node) and the output terminal. The P channel device is a weak device which is biased "on." Selection signals are applied to the gates of the N channel devices. When high valued inputs equal to Vcc, which is typically five volts, are placed on the gates of the N channel devices, a low value is transferred to the NAND gate output. When any other signals are placed on the gates of the N channel devices, the P channel device furnishes a high value (equal to the internal voltage supply value, which is typically either five volts or twelve volts) to the output of the NAND gate. The output of the NAND gate is connected to the input of an inverter joined between the internal voltage supply and ground whose output drives the wordline of the array. The type of NAND gate described is referred to as a ratioed NAND gate.
One reason a ratioed NAND gate is used in the decoding circuitry associated with the wordlines of EPROM and similar arrays is that these arrays operate with both the normal source voltage (five volts) and with the higher source voltage (twelve volts) used to program the array. The typical full CMOS NAND gate having a pair of N channel devices joined in series between ground and an output node and a pair of P channel devices connected in parallel to the source voltage and the output node would not function correctly when the higher source voltage appears as the source voltage unless the CMOS NAND gate includes additional more complex circuitry which is not optimum for high speed decoding. For this reason, the ratioed arrangement using a weak P channel device which is capable of operating with all of the voltages to be expected is used.
However, because the current to the common node to which the row decoders are connected is furnished through a weak P device in a ratioed NAND gate, a relatively small current is available to accomplish the charging of the parasitic capacitance at the common node to which the row decoders are joined. Consequently, the time for deselection at a wordline is longer than is desirable. Slow deselection of the wordline slows down the transition to a newly selected wordline because the previously selected wordline remains selected for a longer period of time. On the other hand, with the increase in the number of memory transistor devices in the arrays, accelerated switching is necessary to overcome wordline delay and provide correct operation of the arrays.
In addition, it is necessary to optimize the voltage level at the point in time when a wordline being selected crosses a wordline being deselected in order to maintain optimum operation of the sense amplifier. If wordline deselection is too slow, this voltage level will be high, and two memory cells will be simultaneously selected. This, in addition to slowing down the access time, will not maintain optimum operation of the sense amplifiers.